The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller feature sizes and more complex circuits than those from the previous generation. Such IC devices are fabricated by patterning a sequence of patterned and un-patterned layers, and the features on successive patterned layers are spatially related to each other. During fabrication, each patterned layer must be aligned with the previous patterned layers with a degree of precision. Pattern alignment techniques typically provide an overlay mark as an alignment structure to achieve alignment between successive layers.
During wafer planarization (such as a polishing process), an overlay mark pattern may be susceptible to damage caused by mechanical polishing that arises due to wafer film thickness deviations. In situations where the polishing process needs extra rework (to meet the desired thickness target), the potential damage caused to the overlay mark may be even greater. Also, if the overlay mark pattern is asymmetrical due to factors such as film uniformity control and mechanical polishing loading effect, relatively large measurement errors may be induced as well.
Therefore, although existing alignment structures have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.